A modified ESD clamp circuit for 90-nm CMOS process

Abstract

In nanoscale CMOS process, integrated circuits (ICs) face serious gate reliability issues such as the damage of electrostatic discharge (ESD). The RC-triggered silicon-controlled rectifier (SCR) is widely studied for the high turn-on efficiency and discharge capability. However, the large gate leakage current of MOS capacitor in the traditional RC network in nanoscale process is not desired. In this work, a modified detection circuit with feedback technique is proposed. The leakage current is reduced to 16 nA at room temperature (25 °C). Under the ESD event, it injects 38 mA trigger current into the p-substrate of SCR. Compared with the previous circuits, the proposed circuit can save area and power consumption while achieving the same performance. The simulation result shows that this clamp circuit can be used in industry.

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